As the High-Definition Multimedia Interface (HDMI) becomes more and more ubiquitous, the number of HDMI ports on consumer electronic devices continues to increase. However, in devices having multiple HDMI ports not all of the input/output (I/O) ports may be physically located near the HDMI receiver/transmitter chip. This may occur, for example, with the use of side and/or front HDMI I/O ports. Unfortunately, due to compliance testing requirements, it is often difficult to merely string a copper connection from the HDMI receiver/transmitter chip to such remotely-located HDMI I/O ports. Such compliance testing typically includes display data channel (DDC) bus capacitance, Transition Minimized Differential Signaling (TMDS) line characteristic impedance and consumer electronics control (CEC) bus capacitance.
One solution has been to install a buffer chip to isolate the internal copper connection between the HDMI receiver/transmitter chip and the HDMI port itself. This has the effect of reducing signal attenuation caused by the long cable run between the remotely-located HDMI port(s) and the HDMI receiver/transmitter chip. However, in order to function correctly, such buffer chips have to be detected and controlled by the device's main processor. As a result, a significant amount of processing overhead tends to be added to the main processor. Also, additional control lines have to be fanned out from the main processor to the buffer chip, thereby adding to the complexity and expense of the system. Thus, what is needed is an improved HDMI receiver/transmitter chipset.